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1 compact synchronous buck regulators isl8002, isl8002a, ISL80019, ISL80019a the isl8002, isl8002a, ISL80019 and ISL80019a are highly efficient, monolithic, synchronous step-down dc/dc converters that can deliver up to 2a of cont inuous output current from a 2.7v to 5.5v input supply. they use peak current mode control architecture to allow very low duty cycle operation. they operate at either 1mhz or 2mhz switching frequency, thereby providing superior transient response and allowing for the use of small inductors. they also have excellent stability and provide both internal and external compensation options. the isl8002, isl8002a, ISL80019 and ISL80019a integrate very low r ds(on) mosfets in order to maximize efficiency. in addition, since the high-side mosf et is a pmos, the need for a boot capacitor is eliminated, thereby reducing external component count. they can operate at 100% duty cycle (at 1mhz) with a dropout of 200mv at 2a output current. these devices can be configured for either pfm (discontinuous conduction) or pwm (continuous conduction) operation at light load. pfm provides high efficiency by reducing switching losses at light loads and pwm reduces noise susceptibility and rf interference. these devices are offered in a space saving 8 pin 2mmx2mm tdfn lead free package with exposed pad for improved thermal performance. the complete converter occupies less than 0.10in 2 area. features ?v in range 2.7v to 5.5v ?v out range is 0.6v to v in ?i out maximum is 1.5a or 2a (see table 1 on page 3 ) ? switching frequency is 1mhz or 2mhz (see table 1 on page 3 ) ? internal or external compensation option ? selectable pfm or pwm operation option ? overcurrent and short circuit protection ? over-temperature/thermal protection ?v in undervoltage lockout and v out overvoltage protection ? up to 95% peak efficiency applications ? general purpose point of load dc/dc ? set-top boxes and cable modems ?fpga power ? dvd, hdd drives, lcd panels, tv related literature ? see an1803 , ?1.5a/2a low quiescent current high efficiency synchronous buck regulator? figure 1. typical application circuit configuration (internal compensation option) figure 2. efficiency vs load f sw = 1mhz, v in = 3.3v, mode = pfm, t a = +25c vin en mode pg phase comp pgnd fb 1 3 2 4 8 6 7 5 r2 vout 100k ? 1% l1 200k ? 1% c1 22 f 1.2 h 22 f 22 f c5 c6 r1 +0.6v gnd vin gnd en pg isl8002 pad 9 +2.7v ?+5.5v +1.8v/2a r 1 r 2 v o vfb ------------ 1 ? ?? ?? = (eq. 1) 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. july 31, 2014 fn7888.4
isl8002, isl8002a, ISL80019, ISL80019a 2 fn7888.4 july 31, 2014 submit document feedback table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pfm mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 short-circuit protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 negative current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 enable, disable, and soft-start up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 discharge mode (soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 100% duty cycle (1mhz version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power derating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output inductor and capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 loop compensation design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
isl8002, isl8002a, ISL80019, ISL80019a 3 fn7888.4 july 31, 2014 submit document feedback table 1. summary of key differences part# i out (max) (a) f sw (mhz) v in range (v) v out range (v) package size ISL80019 1.5 1 2.7 to 5.5 0.6 to 5.5 8 pin 2mmx2mm tdfn ISL80019a 1.5 2 isl8002 2 1 isl8002a 2 2 note: in this datasheet, the parts in the ta ble above are collectively called "device". table 2. component value selection table v out (v) c1 (f) c5, c6 (f) c4 (pf) l1 (h) r1 (k ) r2 (k ) 0.8 22 22 22 1.0~2.2 33 100 1.2 22 22 22 1.0~2.2 100 100 1.5 22 22 22 1.0~2.2 150 100 1.8 22 22 22 1.0~3.3 200 100 2.5 22 22 22 1.5~3.3 316 100 3.3 22 22 22 1.5~4.7 450 100
isl8002, isl8002a, ISL80019, ISL80019a 4 fn7888.4 july 31, 2014 submit document feedback pin configuration isl8002, isl8002a, ISL80019, ISL80019a (8 ld 2x2 tdfn) top view pad 1 3 4 vin mode comp 2 fb pgnd pg en 7 5 6 8 phase pad pin 9 thermal (gnd) pin descriptions pin # pin name pin description 1 vin the input supply for the power stage of the pwm regulator an d the source for the internal linear regulator that provides bias for the ic. place a minimum of 10f ceramic capacitance from vin to gnd and as close as possible to the ic for decoupling. 2 en device enable input. when the voltage on this pin rises abov e 1.4v, the device is enabled. the device is disabled when the pin is pulled to ground. when the device is disabled, a 100 resistor discharges the ou tput through the phase pin. see figure 3 , ? functional block diagram ? on page 5 for details. 3 mode mode selection pin. connect to logic high or input voltage vin for pwm mode. connect to logic low or ground for pfm mode. there is an internal 1m pull-down resistor to prevent an undefined logic state in case the mode pin is left floating, however, it is not recomme nded to leave this pin floating. 4 pg power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation limits. there is an internal 5m internal pull-up resistor on this pin. 5 comp comp is the output of the error amplifier. when comp is tied high to vin, compensation is internal. when comp is connected with a series resistor and capaci tor to gnd, compensation is external. see ? loop compensation design ? on page 20 for more detail. 6 fb feedback pin for the regulator. fb is the negative input to the voltage loop error amplifier. the output voltage is set by an external resistor divider connected to fb. in addition, the power-good pwm regulator?s power-good and undervoltage protection circuits use fb to monitor the output voltage. 7 pgnd power and analog ground connections. connect directly to the board ground plane. 8 phase power stage switching node for output voltage regulation. co nnect to the output inductor. this pin is discharged by an 100 resistor when the device is disabled. see figure 3 , ? functional block diagram ? on page 5 for details. 9thermal pad (t-pad) power ground. this thermal pad provides a return path for the power stage and switching currents, as-well-as a thermal path for removing heat from the ic to the board. place thermal vias to the pgnd plane in this pad.
isl8002, isl8002a, ISL80019, ISL80019a 5 fn7888.4 july 31, 2014 submit document feedback functional block diagram phase + + csa + + ocp skip + + + slope comp slope soft start soft- eamp comp pwm/pfm logic controller protection hs driver fb + 0.85*vref pg shutdown vin pgnd zero-cross sensing scp + 0.3v en shutdown 1ms delay 27pf 200k 3pf 6k - - - - - - - comp 100 shutdown vref + neg current sensing p n + - uv 1.15*vref mode 5m vin * bandgap * please see "comp" pin in the ?pin descriptions? table on for more details. figure 3. functional block diagram oscillator by default, when comp is tied to vin, the voltage loop is internally compensated with the 27pf and 200k rc network. ov page 4
isl8002, isl8002a, ISL80019, ISL80019a 6 fn7888.4 july 31, 2014 submit document feedback ordering information part number (notes 1, 2, 3) tape and reel quantity part marking technical specifications temp. range (c) package tape and reel (pb-free) pkg. dwg. # isl8002irz-t 1000 002 2a, 1mhz -40 to +85 8 ld tdfn l8.2x2c isl8002irz-t7a 250 002 2a, 1mhz -40 to +85 8 ld tdfn l8.2x2c isl8002airz-t 1000 02a 2a, 2mhz -40 to +85 8 ld tdfn l8.2x2c isl8002airz-t7a 250 02a 2a, 2mhz -40 to +85 8 ld tdfn l8.2x2c ISL80019irz-t 1000 019 1.5a, 1mhz -40 to +85 8 ld tdfn l8.2x2c ISL80019irz-t7a 250 019 1.5a, 1mhz -40 to +85 8 ld tdfn l8.2x2c ISL80019airz-t 1000 19a 1.5a, 2mhz -40 to +85 8 ld tdfn l8.2x2c ISL80019airz-t7a 250 19a 1.5a, 2mhz -40 to +85 8 ld tdfn l8.2x2c isl8002frz-t 1000 02f 2a, 1mhz -40 to +125 8 ld tdfn l8.2x2c isl8002frz-t7a 250 02f 2a, 1mhz -40 to +125 8 ld tdfn l8.2x2c isl8002afrz-t 1000 2af 2a, 2mhz -40 to +125 8 ld tdfn l8.2x2c isl8002afrz-t7a 250 2af 2a, 2mhz -40 to +125 8 ld tdfn l8.2x2c ISL80019frz-t 1000 19f 1.5a, 1mhz -40 to +125 8 ld tdfn l8.2x2c ISL80019frz-t7a 250 19f 1.5a, 1mhz -40 to +125 8 ld tdfn l8.2x2c ISL80019afrz-t 1000 9af 1.5a, 2mhz -40 to +125 8 ld tdfn l8.2x2c ISL80019afrz-t7a 250 9af 1.5a, 2mhz -40 to +125 8 ld tdfn l8.2x2c isl8002eval1z evaluation board isl8002aeval1z evaluation board ISL80019aeval1z evaluation board ISL80019eval1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl8002 , isl8002a , ISL80019 , ISL80019a . for more information on msl please see techbrief tb363 .
isl8002, isl8002a, ISL80019, ISL80019a 7 fn7888.4 july 31, 2014 submit document feedback absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v (dc) or 7v (20ms) phase . . . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6v (dc) or 7v (20ms) en, comp, pg, mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v junction temperature range at 0a . . . . . . . . . . . . . . . . . . . . . . . . . .+150c recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 2a junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c thermal resistance (typical, notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 2x2 tdfn package . . . . . . . . . . . . . . . . . . . 71 7 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t j = -40c to +125c, v in = 2.7v to 5.5v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )units input supply v in undervoltage lockout threshold v uvlo rising, no load 2.5 2.7 v falling, no load 2.2 2.4 v quiescent supply current i vin mode = pfm (gnd), f sw = 2mhz, no load at the output 35 60 a mode = pwm (vin), f sw = 1mhz, no load at the output 7 15 ma mode = pwm (vin), f sw = 2mhz, no load at the output 10 22 ma shut down supply current i sd mode = pfm (gnd), v in = 5.5v, en = low 5 10 a output regulation feedback voltage v fb 0.595 0.600 0.605 v t j = -40c to +125c 0.589 0.605 v vfb bias current i vfb v fb = 2.7v. t j = -40c to +125c -120 50 350 na line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) t j = -40c to +125c -0.2 -0.05 0.1 %/v load regulation see note 7 < -0.2 %/a soft-start ramp time cycle 1ms protections positive peak current li mit iplimit 2a application 3 3.5 4 a 1.5a application 2.1 2.5 2.9 a peak skip limit i skip v in = 3.6, v out = 1.8v (see ? applications information ? on page 19 for more detail) 450 ma zero cross threshold -170 -70 30 ma negative current limit inlimit -2.3 -1.5 -1 a thermal shutdown temperature rising 150 c
isl8002, isl8002a, ISL80019, ISL80019a 8 fn7888.4 july 31, 2014 submit document feedback thermal shutdown hysteres is temperature falling 25 c compensation error amplifier trans-conductance comp tied vin 40 a/v comp with rc 120 a/v trans-resistance rt 0.24 0.3 0.40 lx p-channel mosfet on-resistance v in = 5v, i o = 200ma 117 m n-channel mosfet on-resistance v in = 5v, i o = 200ma 86 m lx maximum duty cycle 100 ? lx minimum on-time mode = pwm (high) 1mhz 60 80 ns oscillator nominal switching frequency f sw isl8002, ISL80019 850 1000 1150 khz isl8002a, ISL80019a 1700 2000 2300 khz pg output low voltage 1ma sinking current 0.3 v delay time (rising edge) 0.5 1 2 ms pgood delay time (falling edge) 15 s pg pin leakage current pg = v in 0.01 0.1 a ovp pg rising threshold 110 115 120 % ovp pg hysteresis 5% uvp pg rising threshold 80 85 90 % uvp pg hysteresis 5% en and mode logic logic input low 0.4 v logic input high 1.4 v logic input leakage current i mode pulled up to 5.5v 5.5 8 a notes: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 7. not tested in production. characterized using evaluation board. refer to figures 12 through 14 load regulation diagrams. +105c t a represents near worst case operating point. electrical specifications t j = -40c to +125c, v in = 2.7v to 5.5v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )units
isl8002, isl8002a, ISL80019, ISL80019a 9 fn7888.4 july 31, 2014 submit document feedback typical performance curves figure 4. efficiency vs load f sw = 2mhz, v in = 3.3v, mode = pfm, t a = +25c figure 5. efficiency vs load f sw = 2mhz, v in = 3.3v, mode = pwm, t a = +25c figure 6. efficiency vs load f sw = 1mhz, v in = 3.3v, mode = pfm, t a = +25c figure 7. efficiency vs load f sw = 1mhz, v in = 3.3v, mode = pwm, t a = +25c figure 8. efficiency vs load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 9. efficiency vs load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out efficiency (%) 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.2v out 1.5v out 1.8v out 2.5v out 0.9v out 3.3v out efficiency (%) output load (a) 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.9v out 3.3v out
isl8002, isl8002a, ISL80019, ISL80019a 10 fn7888.4 july 31, 2014 submit document feedback figure 10. efficiency vs load f sw = 1mhz, v in = 5v, mode = pfm, t a = +25c figure 11. efficiency vs load f sw = 1mhz, v in = 5v, mode = pwm, t a = +25c figure 12. load regulation, t a = +105c, 2.7v in , 0.6v out , 1mhz figure 13. load regulation, t a = +105c, 3.3v in , 0.6v out , 1mhz figure 14. load regulation, t a = +105, 5.5v in , 0.6v out , 1mhz typical performance curves (continued) 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out 3.3v out 1.0 efficiency (%) 40 50 60 70 80 90 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) 1.2v out 1.5v out 1.8v out 2.5v out 0.8v out 0.9v out 3.3v out efficiency (%) -0.6 -0.5 -0.4 -0.3 -0.2 0.0 0.1 0 0.5 1.0 1.5 2.0 load current -0.1 load regulation (%) average high low 6 sigma -0.6 -0.5 -0.3 0.0 0.1 0 0.5 1.0 1.5 2.0 -0.2 -0.1 -0.4 load current load regulation (%) average high low 6 sigma -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0 0.5 1.0 1.5 2.0 average high low 6 sigma load current load regulation (%)
isl8002, isl8002a, ISL80019, ISL80019a 11 fn7888.4 july 31, 2014 submit document feedback figure 15. v out regulation vs load, f sw = 2mhz, v out = 0.9v, t a = +25c figure 16. v out regulation vs load, f sw = 2mhz, v out = 1.2v, t a = +25c figure 17. v out regulation vs load, f sw = 2mhz, v out = 1.5v, t a = +25c figure 18. v out regulation vs load, f sw = 2mhz, v out = 1.8v, t a = +25c figure 19. v out regulation vs load, f sw = 2mhz, v out = 2.5v, t a = +25c figure 20. v out regulation vs load, f sw = 2mhz, v out = 3.3v, t a = +25c typical performance curves (continued) 0.895 0.900 0.905 0.910 0.915 0.920 0.925 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output voltage (v) output load (a) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 1.200 1.205 1.210 1.215 1.220 1.225 1.230 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output voltage (v) output load (a) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 1.490 1.495 1.500 1.505 1.510 1.515 1.520 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output voltage (v) output load (a) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 1.780 1.785 1.790 1.795 1.800 1.805 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 o u t p u t v o l t a g e ( v ) output load (a) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 1.810 2.475 2.480 2.485 2.490 2.495 2.500 2.505 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) output voltage (v) 5v in pfm 5v in pwm 3.3v in pwm 3.3v in pfm 3.305 3.310 3.315 3.320 3.325 3.330 3.335 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 output load (a) 5v in pfm mode 5v in pwm mode output voltage (v)
isl8002, isl8002a, ISL80019, ISL80019a 12 fn7888.4 july 31, 2014 submit document feedback figure 21. start-up at no load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 22. start-up at no load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 23. shutdown at no load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 24. shutdown at no load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 25. start-up at 2a load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 26. shutdown at 2a load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c typical performance curves (continued) lx 5v/div v out 1v/div ven 1v/div pg 5v/div 1ms/div lx 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div lx 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div 1ms/div lx 5v/div v out 1v/div ven 2v/div pg 5v/div lx 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div lx 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div
isl8002, isl8002a, ISL80019, ISL80019a 13 fn7888.4 july 31, 2014 submit document feedback figure 27. start-up at 2a load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 28. shutdown at 2a load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 29. start-up at 1.5a load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 30. shutdown at 1.5a load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 31. start-up at 1.5a load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 32. shutdown at 1.5a load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c typical performance curves (continued) lx 5v/div vout 1v/div ven 2v/div pg 5v/div 1ms/div lx 5v/div v out 1v/div ven 2v/div pg 5v/div 1ms/div ven 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div ven 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div p l a c e h o l d e r ven 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div ven 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div
isl8002, isl8002a, ISL80019, ISL80019a 14 fn7888.4 july 31, 2014 submit document feedback figure 33. start-up v in at 2a load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 34. start-up v in at 2a load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 35. shutdown v in at 2a load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 36. shutdown v in at 2a load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 37. start-up v in at no load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 38. start-up v in at no load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c typical performance curves (continued) 500s/div v in 5v/div v out 1v/div i l 1a/div pg 5v/div 500s/div v in 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div v in 5v/div v out 1v/div i l 1a/div pg 5v/div 1ms/div v in 5v/div v out 1v/div i l 1a/div pg 5v/div 500s/div lx 5v/div v out 1v/div v in 5v/div pg 5v/div 500s/div lx 5v/div v out 1v/div v in 5v/div pg 5v/div
isl8002, isl8002a, ISL80019, ISL80019a 15 fn7888.4 july 31, 2014 submit document feedback figure 39. shutdown v in at no load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 40. shutdown v in at no load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 41. jitter at no load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 42. jitter at full load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 43. steady state at no load f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 44. steady state at no load f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c typical performance curves (continued) 100ms/div lx 5v/div v out 1v/div v in 5v/div pg 5v/div 50ms/div lx 5v/div v out 1v/div v in 5v/div pg 5v/div 10ns/div lx 1v/div 10ns/div lx 1v/div 50ms/div lx 5v/div v out 20mv/div i l 0.5a/div 500ns/div lx 5v/div v out 10mv/div i l 0.5a/div
isl8002, isl8002a, ISL80019, ISL80019a 16 fn7888.4 july 31, 2014 submit document feedback figure 45. load transient f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 46. load transient f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 47. output short-circuit f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 48. overcurrent protection f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c figure 49. pfm to pwm transition f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 50. pwm to pfm transition f sw = 2mhz, v in = 5v, mode = pwm, t a = +25c typical performance curves (continued) 200s/div v out ripple 50mv/div i l 1a/div 200s/div v out ripple 50mv/div i l 1a/div 5s/div v out 1v/div i l 2a/div pg 5v/div lx 5v/div 500s/div v out 0.5v/div i l 1a/div pg 5v/div v out ripple 20mv/div i l 2a/div lx 5v/div 2s/div 675ma mode transition, completely enter to pwm at 770ma v out ripple 20mv/div i l 1a/div lx 5v/div 2s/div back to pfm at 121ma
isl8002, isl8002a, ISL80019, ISL80019a 17 fn7888.4 july 31, 2014 submit document feedback theory of operation the device is a step-down switching regulator optimized for battery powered applications. it operates at high switching frequency (1mhz or 2mhz), which enables the use of smaller inductors resulting in small form factor, while also providing excellent efficiency. further, at light loads while in pfm mode, the regulator reduces the switching frequency, thereby minimizing the switching loss and maximizing battery life. the quiescent current when the output is not loaded is typically only 35a. the supply current is typically only 5a when the regulator is shut down. pwm control scheme pulling the mode pin hi (>2.5v) forces the converter into pwm mode, regardless of output current. the device employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and puls e-by-pulse current limiting. see ? functional block diagram ? on page 5 . the current loop consists of the oscillator, the pwm comparator , current sensing circuit and the slope compensation for the current loop stability. the slope compensation is 900mv/ts, which changes with frequency. the gain for the current sensing circuit is typically 300mv/a. the control reference for the current loops comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier cs a and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-fet and turn on the n-channel mosfet. the n-fet stays on until the end of the pwm cycle. figure 53 shows the typical operating waveforms during the pwm operatio n. the dotted lines illustrate the sum of the slope compensati on ramp and the current-sense amplifier?s csa output. the output voltage is regulated by controlling the v eamp voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that co nverts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 200k rc network. the maximum eamp voltage output is precisely clamped to 1.6v. pfm mode pulling the mode pin lo (<0.4v) forces the converter into pfm mode. the device enters a pulse-skipping mode at light load to minimize the switching loss by re ducing the switching frequency. figure 54 illustrates the skip-mode operation. a zero-cross sensing circuit shown in figure 54 monitors the n-fet current for zero crossing. when 16 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. during the eight detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. figure 51. overvoltage protection f sw = 2mhz, v in = 5v, mode = pfm, t a = +25c figure 52. over-temperature protection f sw = 2mhz, v in = 5v, mode = pwm, t a = +163c typical performance curves (continued) 10s/div lx 5v/div v out 2v/div i l 2a/div pg 5v/div 1ms/div v out 0.5v/div pg 2v/div figure 53. pwm operation waveforms v eamp v csa duty cycle i l v out
isl8002, isl8002a, ISL80019, ISL80019a 18 fn7888.4 july 31, 2014 submit document feedback once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator as shown in the ? functional block diagram ? on page 5 . each pulse cycle is still synchronized by the pwm clock. the p-fet is tu rned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak skip current limit value. then the inductor current is discharges to 0a and stays at zero. the internal clock is disabled. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-fet will be turned on again at the rising edge of the internal clock as it repe ats the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in the ? functional block diagram ? on page 5 . the current sensing circuit has a gain of 300mv/a, from the p-fet current to the csa output. when the csa output reaches a threshold, the ocp comparator is tripped to turn off the p-fet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. if the overcurrent condition goes away, the output will resume back into regulation point. short-circuit protection the short-circuit protection (scp) comparator monitors the vfb pin voltage for output short-circ uit protection. when the vfb is lower than 0.3v, the scp comparat or forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start-up or an output short-circuit event. negative current protection similar to the overcurrent, the ne gative current protection is realized by monitoring the current across the low-side n-fet, as shown in the ? functional block diagram ? on page 5 . when the valley point of the inductor current reaches -1.5a for 2 consecutive cycles, both p-fet and n-fet shut off. the 100 in parallel to the n-fet will activate discharging the output into regulation. the control will begin to switch when output is within regulation. the regulator will be in pfm for 20s before switching to pwm if necessary. pg pg is an output of a window comp arator that continuously monitors the buck regulator output voltage. pg is actively held low when en is low and during the buck regulator soft-start period. after 1ms delay of the soft-start period, pg beco mes high impedance as-long-as the output voltage is within nominal regulation voltage set by vfb. when vfb drops 15% below or raises 15% above the nominal regulation voltage, the device pulls pg low. any fault condition forces pg low until the fault condition is cleared by attempts to soft-start. there is an internal 5m pull-up resistor to fit most applications. an external resistor can be added from pg to vin for more pull-up strength. uvlo when the input voltage is below th e undervoltage lock-out (uvlo) threshold, the regulator is disabled. enable, disable, and soft-start up after the vin pin exceeds its rising por trip point (nominal 2.7v), the device begins operation. if the en pin is held low externally, nothing happens until this pin is released. once the en is released and above the logic th reshold, the internal default soft-start time is 1ms. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the outputs discharge to gnd through an internal 100 switch. 100% duty cycle (1mhz version) the device features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the device can no longer maintain th e regulation at the output, the regulator completely turns on the p-fet. the maximum dropout voltage under the 100% duty cycle operation is the product of the load current and the on-resistance of the p-fet. clock i l v out nominal +1.5% nominal pfm current limit 0 16 cycles pwm pfm nominal -1.5% pwm load current figure 54. skip mode operation waveforms
isl8002, isl8002a, ISL80019, ISL80019a 19 fn7888.4 july 31, 2014 submit document feedback thermal shutdown the device has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shutdown. as the temperature drops to +125c, the device resumes operation by stepping through the soft-start. power derating characteristics to prevent the isl8002 from exceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by equation 2 : where pd is the power dissipated by the regulator and ja is the thermal resistance from the junc tion of the die to the ambient temperature. the junction temperature, t j , is given by equation 3 : where t a is the ambient temperature. for the dfn package, the ja is +71c/w. the actual junction temperature should not exceed the absolute maximum junction temperature of +125c when considering the thermal design. the isl8002 delivers full current at ambient temperatures up to +85c; if the thermal impeda nce from the thermal pad maintains the junction temperat ure below the thermal shutdown level, depending on the input voltage/output voltage combination and the switching frequency. the device power dissipation must be reduced to maintain the junction temperature at or below th e thermal shutdown level. figure 55 illustrates the approximate output current derating versus ambient temperature for the isl8002 eval1z kit. applications information output inductor and capacitor selection to consider steady state and transient operations, isl8002a/ISL80019a typically requires a 1.2h and isl8002/ISL80019 typically requires a 2.2h output inductor. higher or lower inductor value can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor ripple current and output voltage ripple, the output inductor value can be increased. it is recommended to set the inductor ripple current to be approximately 30% of the maximum output current for optimized performance. the inductor ripple current can be expressed as shown in equation 4 : the inductor?s saturation current rating needs to be at least larger than the peak current. the device uses internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier (see figure 35 ). the output voltage programming resistor, r 2 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor is typically between 10k and 100k ?? as shown in equation 5 . if the output voltage desired is 0.6v, then r 2 is left unpopulated and r 1 is shorted. there is a leakage current from vin to lx. it is recommended to preload the output with 10a minimum. for better performance, add 22pf in parallel with r 1 ?? check loop analysis before use in application. input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. at least two 22f x5r or x7r ceramic capacitors are a good starting point for th e input capacitor selection. output capacitor selection an output capacitor is required to filter the inductor current. output ripple voltage and transien t response are 2 critical factors when considering output capacitance choice. the current mode control loop allows for the usage of low esr ceramic capacitors and thus smaller board layout . electrolytic and polymer capacitors may also be used. additional consideration applies to ceramic capacitors. while they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter applic ation, these cond itions do not reflect reality. as a result, the actual capacitance may be considerably lower than the advertised value. consult the manufacturers data sheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so this effect can be easily accommodated. the effects of ac t rise pd ??? ja ?? = (eq. 2) t rise t a t rise + ?? = (eq. 3) 0 0.5 1.0 1.5 2.0 2.5 50 60 70 80 90 100 110 120 130 1v 1.5v 2.5v 3.3v temperature (c) output current (v) v in = 5v, olfm figure 55. derating curve vs temperature ? i v o 1 v o v in --------- ? ?? ?? ?? ? lf sw ? -------------------------------------- - = (eq. 4) r 1 r 2 v o vfb ------------ 1 ? ?? ?? = (eq. 5)
isl8002, isl8002a, ISL80019, ISL80019a 20 fn7888.4 july 31, 2014 submit document feedback voltage are not frequently publis hed, but an assumption of ~20% further reduction will generally suffice. the result of these considerations can easily result in an effective capacitance 50% lower than the rated value. nonetheless, they are a very good choice in many applications due to their reliability and extremely low esr. the following equations allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr) = where ? i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: regarding transient response needs, a good starting point is to determine the allowable overshoot in v out if the load is suddenly removed. in this case, energy stored in the inductor will be transferred to c out causing its voltage to rise. after calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. the following equation determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. for an overshoot of 5%, the equation becomes as follows: loop compensation design when comp is not connected to vdd, the comp pin is active for external loop compensation. the isl8002, isl8002a, ISL80019, and ISL80019a use constant frequency peak current mode control architecture to achieve fast loop transient response. an accurate current sensing pilot devi ce in parallel with the upper mosfet is used for peak current control signal and overcurrent protection. the inductor is not considered as a state variable since its peak current is cons tant, and the system becomes a single order system. it is much easier to design a type ii compensator to stabilize the loop than to implement voltage mode control. peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. figure 56 shows the small signal model of the synchronous buck regulator. figure 57 shows the type ii compensator and its transfer function is expressed as equation 10 : where , v outripple ? i 8 ? f sw ? c out -------------------------------------- - = (eq. 6) v outripple ? i*esr = (eq. 7) (eq. 8) c out i out 2 * l v out 2 * v outmax v out ? ?? 2 1 ? ? -------------------------------------------------------------------------------------------- = c out i out 2 * l v out 2 * 1.05 ? 2 1 ? ? ----------------------------------------------------- = (eq. 9) d v in d i l in in i l + 1:d + l i co rc -av(s) d comp v r t fm he(s) + t i (s) k o v t v (s) i l p + 1:d + rc ro -av(s) r t fm he(s) t i (s) k o t(s) ^ ^ v ^ ^ ^ ^ ^ ^ figure 56. small signal model of synchronous buck regulator r lp gain (vloop (s(fi)) - + r 14 v out gm c 8 - + c 7 v ref v fb v comp figure 57. type ii compensator c 4 r 1 r 2 a v s ?? v ? comp v ? fb ---------------- - gm r 2 ? c 7 c 8 + ?? r 1 r 2 + ?? ? -------------------------------------------------------- 1 s ? cz1 ------------ - + ?? ?? 1 s ? cz2 ------------ - + ?? ?? s1 s ? cp1 ------------- + ?? ?? 1 s ? cp2 ------------- + ?? ?? -------------------------------------------------------------- - = = (eq. 10) ? cz1 1 r 14 c 7 ----------------- - ? cz2 1 r 1 c 4 -------------- - = ? cp1 ? c 7 c 8 + r 14 c 7 c 8 ------------------------- - ? cp2 r 1 r 2 + c 4 r 1 r 2 ---------------------- - = ? = , =
isl8002, isl8002a, ISL80019, ISL80019a 21 fn7888.4 july 31, 2014 submit document feedback compensator design goal ?high dc gain ? choose loop bandwidth f c less than 100khz ? gain margin: >10db ? phase margin: >50 the compensator design procedure is as follows: the loop gain at crossover frequency of f c has unity gain. therefore, the compensator resistance r 14 is determined by equation 11 . where gm is the trans-conductance of the voltage error amplifier. compensator capacitors c 7 and c 8 are then given by equations 12 and 13 . an optional zero can boost the phase margin. ? cz2 is a zero due to r 1 and c 4 ? put compensator zero 2 to 5 times f c : example: v in = 5v, v out = 1.8v, i o = 2a, f sw = 1mhz, r 1 =200k ? , r 2 = 100k ? , c out =2x22f/3m , l = 2.2h, f c = 100khz, then compensator resistance r 14 : using the closest standard value for r 14 value is fine (200k ?? . the closest standard values for c 7 and c 8 are also fine. there is approximately 3pf parasitic capacitance from v comp to gnd; therefore, c 8 is optional. use c 7 = 220pf and c 8 = open. use c 4 = 15pf. note that c 4 may increase the loop bandwidth from previously estimated value. figure 58 shows the simulated voltage loop gain. it is shown th at it has 114khz loop bandwidth with 52 phase margin and 10db gain margin. it may be more desirable to achieve more phase margin. this can be accomplished by lowering r 14 by 20% to 50%. layout considerations the pcb layout is a very important converter design step to make sure the designed converter works well. the power loop is composed of the output inductor l?s, the output capacitor c out , the phase?s pins, and the pgnd pin. it is necessary to make the power loop as small as possibl e and the connecting traces among them should be direct, short and wide. the switching node of the converter, the phase pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as closely as possible to the vin pin and the ground of the input and output capacitors should be connected as closely as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 4 vias ground connection within the pad for the best thermal relief. r 14 2 ? f c v o c o r t gm v fb ? --------------------------------- - 26 3 ? 10 f c v o c o ? == (eq. 11) c 7 r o c o r 14 -------------- - v o c o i o r 14 --------------- = = (eq. 12) (eq. 13) c 8 max r c c o r 14 -------------- - 1 ? f s r 14 ------------------ - (, ) = c 4 1 ? f c r 1 --------------- - = (eq. 14) r 14 26 3 ? 10 100khz 1.8v 44 ? f ? ? ? 205k ? == (eq. 15) c 7 1.8v 44 ?? f 2a 200k ? ? ------------------------------- - 198pf = = (eq. 16) c 8 max 3m ? 44 ? f ? 200k ? -------------------------------- - 1 ? 1mhz 200k ? ?? ? ------------------------------------------------ (, ) 1pf 2.3pf (, ) = = (eq. 17) c 4 1 ? 100khz 200k ? ? ------------------------------------------------ = 16pf = (eq. 18) figure 58. simulated loop gain 60 45 30 15 0 -15 -30 100 1k 10k 100k 1m frequency (hz) 180 150 120 90 60 30 0 100 1k 10k 100k 1m frequency (hz) phase ( ) gain (db)
isl8002, isl8002a, ISL80019, ISL80019a 22 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7888.4 july 31, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 31, 2014 fn7888.4 page 18 under overcurrent protection: removed a text, which read ?after the hiccup mode expires?. added ISL80019aeval1z and ISL80019eval1z to ordering information table on page 6 . november 26, 2013 fn7888.3 added eval boards to ?ordering information? on page 6. added curve and ?power derating characteristics? on page 19. july 30, 2013 fn7888.2 updated ordering information table on page 6. added figures 12, 13 and 14 to ?typical performance curves? on page 9. electrical specifications on page 7 under output regulation section removed duplicate of "t j = -40c to +125c" from vfb bias current to in place line regulation. june 13, 2013 functional block diagram on page 5 - changed vfb to vref changed part number in ordering information on page 6 from ISL80019frz-t to ISL80019fz-t changed on page 7 recommend operating cond itions the word "ambient" to "junction" changed in electrical spec on page 7 conditions from ta -40 to +85 to tj -40 to +125 vfb bias current under output regulation test condition from 0.75v and typ from 0.1 to 2.7v min -120 typ 50 max 350 type ii compensator graphic on page 20 - changed vfb to vref may 10, 2013 pin descriptions on page 4: en se ction, changed pin rises from 0.6v to 1.4v. january 7, 2013 fn7888.1 initial release.
isl8002, isl8002a, ISL80019, ISL80019a 23 fn7888.4 july 31, 2014 submit document feedback package outline drawing l8.2x2c 8 lead thin dual flat no-lead plastic package (tdfn) with e-pad rev 0, 07/08 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2.00 2.00 ( 6x0.50 ) 2.00 2.00 ( 8x0.30 ) ( 8x0.20 ) ( 8x0.30 ) 0.50 0.800.050 exp.dap 0.25 1.450.050 exp.dap ( 8x0.25 ) 0.80 1.45 pin #1 index area b 0.10 m a c 0 . 75 ( 0 . 80 max) c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 6 index area pin 1 6 (4x) 0.15 a b 1 package outline 8

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